1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an In-Plane Switching (IPS) mode LCD device that has an increased luminance and method of fabricating such IPS mode LCD device.
2. Discussion of the Related Art
The liquid crystal molecules for the LCD device have unique characteristics, such that an arrangement direction (i.e., orientation) of the liquid crystal molecules can be controlled by applying a desired level of an electrical field to them. As a result, the liquid crystal molecules become aligned to transmit light, and images can be displayed on the screen. Thus, the LCD device displays images by controlling magnitudes of the electric field applied to the liquid crystal molecules. In addition, the LCD device is sometimes referred to as an active matrix LCD (AM-LCD) device that includes an improved resolution and improved displaying features (i.e., faster response time while displaying the moving images).
Generally, most LCD devices include a thin film transistor (TFT) as a switching element. Further, a related art LCD device includes a first substrate and a second substrate that are facing each other and a liquid crystal layer interposed between the two substrates. The first substrate includes a pixel electrode, and the second substrate includes a color filter layer and a common electrode. The related art LCD device displays images by generating a vertical electric field between the pixel and common electrodes. The related art LCD device using the vertical electric field has an increased light transmittance and an increased aperture ratio. However, the related art LCD device has several problems, such as a narrow viewing angle, low contrast ratio, and other problems. To resolve the above-mentioned problems, an in-plane switching (IPS) mode LCD device having a wide viewing angle is suggested.
FIG. 1 is a cross-sectional view of a related art IPS mode LCD device. As shown in FIG. 1, the related art IPS mode LCD device includes first and second substrates 10 and 40 that are facing each other, and a liquid crystal layer LC interposed between the two substrates. The first and second substrates 10 and 40 may be referred to as an array substrate and a color filter substrate, respectively.
A pixel region P is defined on the first substrate 10. A thin film transistor (TFT) T, a common electrode 18 and a pixel electrode 30 are formed on the first substrate 10 in the pixel region P. The TFT T includes a gate electrode 14 on the first substrate 10, a gate insulating layer 20 over the gate electrode 14, a semiconductor layer 22 over the gate insulating layer 20, and source and drain electrodes 24 and 26 over the semiconductor layer 22. The source and drain electrodes 24 and 26 are separated from each other. The common electrodes 18 and the pixel electrodes 30 are arranged alternating each other and also arranged parallel to each other. The common electrode 18 is formed of a same layer and a same material as the gate electrode 14. The pixel electrode 30 is formed of a same layer and a same material as the source and drain electrodes 24 and 26. The pixel electrode 30 is connected to the TFT T. The liquid crystal layer LC is controlled by a horizontal electric field generated between the common electrode 18 and the pixel electrode 30.
Although not shown in FIG. 1, gate and data lines are formed on the first substrate 10 to define the pixel region P, and a common line is formed on the first substrate 10 to apply voltage to the common electrode 18. The second substrate 40 includes a black matrix 42 and a color filter 44. The black matrix 42 corresponds to the gate line (not shown), the data line (not shown) and the TFT T. The color filter 44 includes sub-color filters 44a and 44b and corresponds to the pixel region P. Each of the sub-color filters 44a and 44b includes one of red R, green G and blue B (not shown) color.
FIG. 2 is a plane view of an array substrate for the related art IPS mode LCD device. As shown in FIG. 2, the gate line 12 and data line 28 are formed on the first substrate 10 to define the pixel region P, and a common line 16 is formed parallel to the gate line 12. The TFT T is formed in the pixel region P and connected to the gate and data lines 12 and 28. The TFT T includes the gate electrode 14, the gate insulating layer 20 (of FIG. 1), the semiconductor layer 22 and the source and drain electrodes 24 and 26. The source and drain electrodes 24 and 26 are separated from each other. The gate electrode 14 extends from the gate line 12 and the source electrode 24 extends from the data line 28. Moreover, the common electrode 18 and the pixel electrode 30 are formed in a comb shape in the pixel region P. The pixel electrode 30 is connected to the TFT T and the combs of the pixel electrode 30 are arranged alternately with the combs of the common electrode 18. The common electrode 18 extends from the common line 16 such that the common electrode 18 is perpendicular to the common line 16. The common and pixel electrodes 18 and 30 are parallel to each other.
The related art IPS mode LCD device including the array substrate of FIG. 2 has an improved viewing angle in the left and right sides. However, the viewing angle in the upper and lower sides, and along the diagonal direction are not improved. To resolve the above problem, another related art IPS mode LCD device (shown in FIG. 3) is suggested. The common and pixel electrodes are aligned in a length-wise direction and a width-wise direction to increase the viewing angle in the upper and lower sides.
FIG. 3 is a plane view of an array substrate for another related art IPS mode LCD device. As shown in FIG. 3, the gate lines 52 and data lines 66 are formed on the substrate 50 to define the pixel region P. The TFT T is formed in the pixel region P and connected to the gate and data lines 52 and 66. The TFT T includes the gate electrode 54, the gate insulating layer (not shown), the semiconductor layer 60 and the source and drain electrodes 62 and 64. The source and drain electrodes 62 and 64 are separated from each other. The gate electrode 54 extends from the gate line 52 and the source electrode 62 extends from the data line 66. Further, the common and pixel electrodes 56 and 72 are formed in the pixel region P. The pixel electrode 72 is connected to the TFT T.
The common electrode 56 is formed of a same layer and a same material as the gate electrode 54. The pixel electrode 72 is formed of a transparent conductive material to increase an aperture ratio. However, the pixel electrode 72 may be formed of a same layer and a same material as the source and drain electrodes 62 and 64. The gate insulating layer (not shown) and a passivation layer (not shown) are disposed between the common electrode 56 and the pixel electrode 72 to prevent the two electrodes from contacting each other.
The common electrode 56 includes a plurality of first common portions 56a, second common portions 56b, and third common portions 56c. As shown in FIG. 3, the plurality of first common portions 56a are disposed in a width-wise direction, and the second and third common portions 56b and 56c are disposed in a length-wise direction. In other words, the plurality of first common portions 56a are disposed parallel to the gate line 52, and the second and third common portions 56b and 56c are disposed parallel to the data line 66. Similarly, the pixel electrode 72 includes a plurality of first pixel portions 72a, second pixel portions 72b, and third pixel portions 72c. The plurality of first pixel portions 72a are disposed in the width-wise direction, and the second and third pixel portions 72b and 72c are disposed in the length-wise direction. The plurality of first pixel portions 72a are parallel to the plurality of first common portion 56a, and the second and third pixel portions 72b and 72c are parallel to the first and second common portions 56b and 56c. 
Since the common and pixel electrodes 56 and 72 are disposed in the width-wise and length-wise directions, the viewing angle in the upper and lower sides is improved. Moreover, when the plurality of first common and pixel portions 56a and 72a are parallel to the gate and data lines 52 and 66, the viewing angle along the diagonal direction is improved.
However, since the common and pixel electrodes 56 and 72 are formed of different layers, a misalignment of layers may result. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3. As shown in FIG. 4, the plurality of first common portions 56a are formed on the substrate 50. The gate insulating layer 58 is formed over the plurality of common portions 56a and the passivation layer 68 is formed over the gate insulating layer 58. The plurality of first pixel portions 72a are formed on the passivation layer 68 and are alternately arranged with the plurality of first common portions 56a. Accordingly, since the plurality of first common portions 56a are formed on the substrate 50 before the plurality of first pixel portions 72a are formed, misalignment is generated during formation of the plurality of first common and first pixel portions 56a and 72a. 
The plurality of first common and first pixel portions 56a and 72a are formed by a mask process (not shown) and the misalignment is generated during the mask process. As shown in FIG. 4, a distance between the first common and pixel portions 56a and 72a is “L” in a normal area NA. However, a distance between the first common and pixel portions 56a and 72a becomes “L-a” in a misalignment area MA. And, “L-a” is less than the “L”.
The related art IPS mode LCD device having the above problems includes decreased image display quality. Further, the array substrate of FIG. 3 includes the common electrode 56 formed of a same opaque material as the gate electrode 54, thus decreasing the luminance.